1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a gate insulating film adjacent to a heterojunction.
2. Description of the Related Art
Silicon Carbide has a dielectric breakdown electric field intensity which is one digit larger than that of silicon. Like silicon, silicon carbide can be thermally oxidized. For these reasons, silicon carbide draws attention as a next-generation semiconductor material. It is highly expected that silicon carbide may be applied particularly to electric power conversion devices. Against this background, there has been proposed a low-loss power transistor with a higher breakdown voltage which is formed of a silicon carbide material. In order for a power transistor to have a low-loss characteristic, it is essential that the transistor have a lower ON resistance. With this taken in consideration, a field effect transistor disclosed in Japanese Patent Application Laid-open Publication No. 2003-318398 has been proposed as an example of a structure of a power transistor which makes it possible to effectively reduce the ON resistance of the power transistor. In the case of this field effect transistor, an N− type silicon carbide epitaxial region is formed on an N+ type silicon carbide substrate, and a polysilicon layer whose bandgap is different from that of silicon carbide is formed on a predetermined area in the silicon carbide epitaxial region. In addition, the polysilicon layer forms a heterojunction with the silicon carbide epitaxial region. Furthermore, a gate electrode is arranged adjacent to this heterojunction portion with a gate insulating film in between.